A time-to-digital converter implements conversion from time signals to digital signals by sampling and quantizing time intervals. The time-to-digital converter is widely used in such fields as space exploration, high energy physics, and test equipment, and in recent years, the time-to-digital converter is greatly promoted as a key module in a digital phase locked loop (DPLL).
A structure of a time-to-digital converter in a digital phase locked loop includes a reference clock signal input end and a sampling clock signal input end. After a reference clock signal is input, the reference clock signal passes through multiple stages of same delayers. When a first stage of delayer is passed through, a delayed signal having a delay duration of t is output (t is a degree of precision of the time-to-digital converter), and the delayed signal that is output by the first stage of delayer is input to a second stage of delayer, to obtain a delayed signal having a delay duration of two times of t. By analogy, a delayed signal obtained by an (i−1)th stage of delayer is input to an it stage of delayer, to obtain a delayed signal having a delay duration of i times of t. A sampling clock signal separately samples the series of obtained delayed signals, to obtain a series of output signals. A dynamic range of the time-to-digital converter is t×i, and if t remains unchanged and the time-to-digital converter needs to obtain a large dynamic range, a quantity of stages of delayers needs to be increased. However, an increase in the quantity of stages of delayers directly results in an increase in a quantity of stages of the time-to-digital converter, and the area and power consumption of the time-to-digital converter both increase accordingly.